1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, it relates to a semiconductor device including a MOS transistor having a gate oxide film prevented from dielectric breakdown and a method of manufacturing the same.
2. Description of the Background Art
A semiconductor device (hereinafter referred to as an SOI device) having an SOI (silicon on insulator) structure formed on an SOI substrate including a buried oxide film and an SOI layer arranged on a silicon substrate, which can reduce parasitic capacitance and operate at a high speed with lower power consumption, is employed for a portable device or the like.
FIG. 41 shows a partially fragmented sectional structure of an exemplary SOI device 70 electrically isolating MOS transistors by trench isolation.
Referring to FIG. 41, an SOI substrate includes a buried oxide film 2 and an SOI layer 3 arranged on a silicon substrate 1, and an N-channel MOS transistor (NMOS transistor) N1 and a P-channel MOS transistor (PMOS transistor) P1 are arranged on the SOI layer 3 while an isolation oxide film 4 completely electrically isolates these MOS transistors N1 and P1 from each other. The isolation oxide film 4 is so arranged as to enclose the NMOS transistor N1 and the PMOS transistor P1.
Each of the NMOS transistor N1 and the PMOS transistor P1 is formed by source/drain regions SD and a channel forming region CH formed in the SOI layer 3, a gate oxide film GO formed on the channel forming region CH, a gate electrode GT formed on the gate oxide film GO and side wall oxide films SW covering the side surfaces of the gate electrode GT.
Thus, in the SOI device 70, the NMOS transistor N1 and the PMOS transistor P1 are not only independent of each other in the SOI layer 3 due to the isolation oxide film 4 but also completely isolated from other semiconductor elements etc., whereby no latch-up takes place in principle in these transistors N1 and P1.
When manufacturing an SOI device having a CMOS transistor, therefore, the minimum isolation width decided by a microlithography can be used and the chip area can be advantageously reduced. However, a substrate floating effect causes various problems such that carriers (holes in an NMOS transistor) generated by impact ionization are collected in the channel forming region to result in kinks or deteriorate an operating withstand voltage and such that instability of the potential of the channel forming region results in frequency dependency of a delay time.
In this regard, a partial trench isolation structure has been devised. FIG. 42 is a partially fragmented sectional view showing an SOI device 80 having such a partial trench isolation structure (PTI structure).
Referring to FIG. 42, an NMOS transistor N1 and a PMOS transistor P1 are arranged on an SOI layer 3 while a partial isolation oxide film 5 having a well region WR arranged on its lower portion isolates the NMOS transistor N1 and the PMOS transistor P1 from each other. The partial isolation oxide film 5 is so arranged as to enclose the NMOS transistor N1 and the PMOS transistor P1.
With respect to the partial isolation oxide film 5, a structure such as that of the isolation oxide film 4 in the SOI device 70 completely electrically isolating elements with a trench oxide film reaching the buried oxide film 2 is referred to as a full trench isolation structure (FTI structure), and the oxide film is referred to as a full isolation oxide film.
While the partial isolation oxide film 5 isolates the NMOS transistor N1 and the PMOS transistor P1 from each other, carriers are movable through the well region WR on the lower portion of the partial isolation oxide film 5 and can be prevented from being collected in channel forming regions while the potential of the channel forming regions can be fixed through the well region WR, whereby no problems are caused by a substrate floating effect.
Whether an SOI device employs the PTI structure or the FTI structure, however, new manufacturing steps must be added for increasing the thickness of gate oxide films in order to improve reliability of MOS transistors and adjusting the quantity of an impurity injected into channels in order to reduce threshold voltages.
A method of manufacturing an SOI device 90 having a PTI structure improving reliability of MOS transistors is now described with reference to FIGS. 43 to 50.
First, an SOI substrate structured by a silicon substrate 1, a buried oxide film 2 and an SOI layer 3, formed by a SIMOX method forming the buried oxide film 2 by oxygen ion implantation or a bonding method is prepared. In general, the thickness of the SOI layer 3 is 50 to 200 nm, and the thickness of the buried oxide film 2 is 100 to 400 nm. As shown in FIG. 43, an oxide film 6 of about 10 to 30 nm (100 to 300 xc3x85) in thickness is formed on the SOI substrate by CVD or thermal oxidation, and a nitride film 7 of 30 to 200 nm (300 to 2000 xc3x85) in thickness is formed thereon. Then, a resist mask RM1 is formed on the nitride film 7 by patterning. The resist mask RM1 has an opening for forming a trench.
Then, the resist mask RM1 is employed as a mask for patterning the nitride film 7, the oxide film 6 and the SOI layer 3 by etching thereby forming a partial trench TR in the SOI layer 3, as shown in FIG. 44. In this etching, etching conditions are so adjusted as not to completely etch the SOI layer 3 and expose the buried oxide film 2 but to leave the SOI layer 3 on the bottom of the trench TR in a prescribed thickness.
The partial trench TR1 is formed to extend substantially perpendicularly to the silicon substrate 1 with a prescribed width, whereby element isolation can be performed while maintaining refinement without deteriorating the degree of integration.
In a step shown in FIG. 45, an oxide film of about 500 nm (5000 xc3x85) in thickness is deposited, a portion up to an intermediate portion of the nitride film 7 is polished by CMP (chemical mechanical polishing), and thereafter the nitride film 7 and the oxide film 6 are removed thereby forming a partial isolation oxide film 5. It is assumed here that the region located on the left side of the partial isolation oxide film 5 in FIG. 45 is a first region R1 for forming a transistor having a low threshold voltage while the region located on the right side of the partial isolation oxide film 5 is a second region R2 for forming a highly reliable transistor having a general threshold voltage.
In a step shown in FIG. 46, an oxide film OX1 is formed on the overall area of the SOI layer 3. The thickness of the oxide film OX1 is 1 to 4 nm (10 to 40 xc3x85). Thereafter a resist mask RM2 is formed to cover the second region R2, and a semiconductor impurity is introduced into the SOI layer 3 of the first region R1 by ion implantation through the oxide film OX1. As to the conditions for this implantation for forming the transistor having a low threshold voltage, boron (B) ions are implanted with energy of 5 to 40 keV and in a dose of 1xc3x971011 to 3xc3x971011/cm2 when forming an NMOS transistor, for example. In advance of this step, boron ions are implanted with energy of 30 to 100 keV and in a dose of 1xc3x971012 to 1xc3x971014/cm2 for forming a well region.
In a step shown in FIG. 47, a resist mask RM3 is formed to cover the first region R1, and a semiconductor impurity is introduced into the SOI layer 3 of the second region R2 by ion implantation through the oxide film OX1. As to the conditions for this implantation for forming the transistor having a general threshold voltage, boron (B) ions are implanted with energy of 5 to 40 keV and in a dose of 3xc3x971011 to 5xc3x971011/cm2 when forming an NMOS transistor, for example.
In a step shown in FIG. 48, a resist mask RM4 is formed to cover the second region R2, and the oxide film OX1 is removed from the first region R1.
The resist mask RM4 is removed and thereafter an oxide film is formed on the overall area in a step shown in FIG. 49. At this time, an oxide film OX2 of 2 to 4 nm (20 to 40 xc3x85) in thickness is formed on the region R1, while the thickness of the oxide film OX1 is increased to define an oxide film OX3 on the region R2. Thereafter a polycrystalline silicon layer (hereinafter referred to as a polysilicon layer) PS1 defining gate electrodes is formed on the overall area.
In a step shown in FIG. 50, the polysilicon layer PS1 and the oxide films OX2 and OX3 are patterned for forming gate electrodes GT1 and GT2 and gate oxide films GO1 and GO2 and forming NMOS transistors N3 and N4 by forming side wall oxide films SW and source/drain layers SD. A well region WR is provided on a lower portion of the partial isolation oxide film 5.
An interlayer isolation film is formed on the NMOS transistors N3 and N4 and a plurality of contact holes reaching the source/drain layers SD through the interlayer isolation film are formed to structure the SOI device 90, while illustration of these elements is omitted.
Thus, the thickness of gate oxide film is generally increased for forming the transistor having high reliability thereby preventing the gate oxide film from dielectric breakdown, with requirement for steps of forming resist masks. When increasing the thickness of the gate oxide film, however, there is a possibility of such a problem that the transistor characteristics are deteriorated.
According to a first aspect of the present invention, a semiconductor device comprises a semiconductor substrate, a plurality of semiconductor elements formed on the semiconductor substrate and a trench isolation oxide film obtained by burying an oxide film in a trench formed in the surface of the semiconductor substrate for electrically isolating the plurality of semiconductor elements by the trench isolation oxide film, while trench isolation oxide film has different contour shapes of the upper edge portion on the left and right edges in a brachydirectional section of the trench isolation oxide film.
In the semiconductor device according to the first aspect of the present invention, the trench isolation oxide film has different contour shapes of the upper edge portion on the left and right edges in the brachydirectional section of the trench isolation oxide film, whereby gate oxide films of MOS transistors formed on the left and right sides of the trench isolation oxide film can have different thicknesses and the shapes of the edge portions of the gate oxide films can be optimized in response to MOS transistors having different specs.
According to a second aspect of the present invention, the semiconductor substrate is an SOI substrate comprising a silicon substrate, a buried oxide film arranged on the silicon substrate and an SOI layer arranged on the buried oxide film, and the trench isolation oxide film is arranged in the surface of the SOI substrate.
In the semiconductor device according to the second aspect, the semiconductor substrate is an SOI substrate and the trench isolation oxide film is arranged in the surface of the SOI substrate, whereby the semiconductor device can attain high reliability while preventing gate oxide films of SOIMOS transistors from dielectric breakdown. Further, only the thickness of the edge portions of the gate oxide films is increased, and hence the transistor characteristics are not deteriorated dissimilarly to the case of increasing the overall thickness of the gate oxide films.
According to a third aspect of the present invention, the trench isolation oxide film has such a contour shape that its upper edge portion projects into the surface of the semiconductor substrate in the form of a bird""s beak.
In the semiconductor device according to the third aspect, the upper edge portion of the trench isolation oxide film has the contour shape projecting into the surface of the semiconductor substrate in the form of a bird""s beak. When the semiconductor elements are MOS transistors, therefore, the thickness of edge portions of gate oxide films is consequently increased by forming the gate oxide films to engage with the bird""s beak of the trench isolation oxide film, and the semiconductor device can attain high reliability while preventing the gate oxide films from dielectric breakdown in the vicinity of edge portions of gate electrodes where an electric field readily concentrates. Further, only the thickness of the edge portions of the gate oxide films is increased, and hence the transistor characteristics are not deteriorated dissimilarly to the case of increasing the overall thickness of the gate oxide films.
According to a fourth aspect of the present invention, the trench isolation oxide film has different shapes on the left and right sides in its brachydirectional section, and combinationally includes a full trench structure reaching the buried oxide film through the SOI layer and a partial trench structure having the SOI layer on its lower portion.
In the semiconductor device according to the fourth aspect, the trench isolation film combinationally has the full trench structure and the partial trench structure, whereby the upper edge portion can readily have different contour shapes on the sides of the full trench structure and the partial trench structure in the process of formation thereof.
According to a fifth aspect of the present invention, the height of a protrusion on a base portion of the upper edge portion projecting in the form of the bird""s beak on the side of the full trench structure is relatively small, and the height of a protrusion on a base portion of the upper edge portion projecting in the form of the bird""s beak on the side of the partial trench structure is relatively large in the trench isolation oxide film.
In the semiconductor device according to the fifth aspect, the height of the protrusion on the base portion of the upper edge portion projecting in the form of the bird""s beak on the side of the full trench structure is relatively small and the height of the protrusion on the base portion of the upper edge portion projecting in the form of the bird""s beak on the side of the partial trench structure is relatively large, whereby the thickness of the edge portion of the gate oxide film can be reduced in the MOS transistor engaging with the full trench structure side so that a gate oxide film suitable for the MOS transistor whose transistor characteristics are set with the characteristics of a parasitic transistor can be obtained while the thickness of the edge portion of the gate oxide film can be increased in the MOS transistor engaging with the partial trench structure side and hence a gate oxide film suitable for a MOS transistor requiring improvement in reliability of the gate oxide film can be obtained.
According to a sixth aspect of the present invention, the length of the upper edge portion projecting in the form of the bird""s beak on the side of the full trench structure is relatively large, and the length of the upper edge portion projecting in the form of the bird""s beak on the side of the partial trench structure is relatively small in the trench isolation oxide film.
In the semiconductor device according to the sixth aspect, the length of the upper edge portion projecting in the form of the bird""s beak on the side of the full trench structure is relatively large and the length of the upper edge portion projecting in the form of the bird""s beak on the side of the partial trench structure is relatively small, whereby the shapes of the edge portions of the gate oxide films can be optimized in response to MOS transistors having different specs.
According to a seventh aspect of the present invention, the trench isolation oxide film has different contour shapes of a base portion of the upper edge portion projecting in the form of the bird""s beak on the side of the partial trench structure between a first inclined portion along a direction separating from the SOI layer and a second inclined portion directed toward the SOI layer, the first inclined portion has a substantially linear contour shape, and the second inclined portion has a contour shape roundedly projecting toward the SOI layer.
In the semiconductor device according to the seventh aspect, the first inclined portion of the upper edge portion on the side of the partial trench structure has a substantially linear contour shape and hence an unnecessary gate material can be prevented from remaining on the surface of the isolation oxide film when removing the gate material in gate electrode formation. Further, the second inclined portion has a contour shape roundedly projecting toward the SOI layer, whereby stress caused in the vicinity of the interface between the SOI layer and the isolation oxide film resulting from heat treatment or oxidation performed in the process of manufacturing the semiconductor device can be relaxed and the SOI layer can be inhibited from formation of crystal defects resulting from such stress.
According to an eighth aspect of the present invention, the trench isolation oxide film has different contour shapes of a base portion of the upper edge portion projecting in the form of the bird""s beak on the side of the partial trench structure between a first inclined portion along a direction separating from the SOI layer and a second inclined portion directed toward the SOI layer, the first inclined portion has a contour shape roundedly depressed toward the SOI layer, and the second inclined portion has a contour shape roundedly projecting toward the SOI layer.
In the semiconductor device according to the eighth aspect, the first inclined portion of the upper edge portion on the side of the partial trench structure has the contour shape roundedly depressed toward the SOI layer, whereby an effect of preventing an unnecessary gate material from remaining on the surface of the isolation oxide film is increased when removing the gate material in gate electrode formation while a step projecting from the main surface of the SOI layer can be reduced by reducing the thickness of the edge portion of the trench isolation oxide film thereby simplifying a step of forming gate electrodes or the like. Further, the second inclined portion has the contour shape roundedly projecting toward the SOI layer, whereby stress caused in the vicinity of the interface between the SOI layer and the isolation oxide film resulting from heat treatment or oxidation performed in the process of manufacturing the semiconductor device can be relaxed and the SOI layer can be inhibited from formation of crystal defects resulting from such stress.
According to a ninth aspect of the present invention, the trench isolation oxide film has such a contour shape that its lower edge portion projects between the SOI layer and the buried oxide film.
In the semiconductor device according to the ninth aspect, the lower edge portion of the trench isolation oxide film has the contour shape projecting between the SOI layer and the buried oxide film, whereby the interfacial state between the SOI layer and the buried oxide film can be improved.
According to a tenth aspect of the present invention, a method of manufacturing a semiconductor device comprises steps of (a) preparing an SOI substrate comprising a silicon substrate, a buried oxide film arranged on the silicon substrate and an SOI layer arranged on the buried oxide film, (b) forming an oxide extension layer on the SOI layer, (c) forming a mask layer having a prescribed opening pattern on the oxide extension layer, (d) forming a trench by selectively removing the SOI layer through the mask layer without passing through the SOI layer from the surface, (e) forming a resist mask having an opening at a first region between a prescribed position at least on the bottom surface of the trench and a first side wall surface in a brachydirectional section, and covering a second region between at least the prescribed position and a second side wall surface in the brachydirectional section, (f) removing the trench to reach the buried oxide film through the resist mask for forming a combined trench having a portion corresponding to the second region being a partial trench having the SOI layer on its lower portion and a portion corresponding to the first region being a full trench passing through the SOI layer, (g) forming a first oxide film on the inner wall of the combined trench by thermally oxidizing the inner wall of the buried trench and the oxide extension layer and (h) forming a trench isolation oxide film combinationally having a full trench structure reaching the buried oxide film through the SOI layer and a partial trench structure having the SOI layer on its lower portion by filling up the combined trench with a second oxide film.
In the method of manufacturing a semiconductor device according to the tenth aspect, a trench isolation oxide film combinationally having a full trench structure reaching the buried oxide film through the SOI layer and a partial trench structure having the SOI layer on its lower portion can be obtained. Further, this trench isolation oxide film has such a contour shape that its upper edge portion projects into the surface of the SOI layer in the form of a bird""s beak while the contour shape differs on the left and right edges in a brachydirectional section.
According to an eleventh aspect of the present invention, the oxide extension layer includes an oxide film arranged on the SOI layer and a polycrystalline silicon layer arranged on the oxide film.
In the method of manufacturing a semiconductor device according to the twelfth aspect, the oxide extension layer includes the oxide film arranged on the SOI layer and the polycrystalline silicon layer arranged on the oxide film, whereby the polycrystalline silicon layer is oxidized in formation of the first oxide film so that the bird""s beak on the upper edge portion of the trench isolation oxide film has a clearer shape.
According to a twelfth aspect of the present invention, the step (h) includes steps of (h-1) forming the second oxide film to fill up the combined trench and cover the overall area on the mask layer, and (h-2) planarizing the second oxide film by chemical mechanical polishing through the mask layer serving as a stopper.
In the method of manufacturing a semiconductor device according to the twelfth aspect, the second oxide film is planarized by chemical mechanical polishing through the mask layer serving as a stopper, whereby the shape of the edge portion of the trench isolation oxide film can be adjusted by adjusting the degree of planarizing.
According to a thirteenth aspect of the present invention, the opening of the resist mask is provided over the first region and a first edge portion of the mask layer adjacent to the first region, and the first edge portion of the mask layer is removed to have a step in association with formation of the combined trench so that the thickness of the mask layer is partially reduced.
In the method of manufacturing a semiconductor device according to the fourteenth aspect, the first edge portion of the mask layer is removed to be thin with the step so that the thickness of the second oxide film is reduced on the portion of the full trench and increased on the portion of the partial trench, whereby such a trench isolation oxide film can be finally obtained that the height of the protrusion on the base portion of the upper edge portion projecting in the form of the bird""s beak is relatively small on the side of the full trench structure and the height of the protrusion on the base portion of the upper edge portion projecting in the form of the bird""s beak is relatively large on the side of the partial trench structure.
According to a fourteenth aspect of the present invention, the resist mask further includes a local opening arranged on at least either a first prescribed region of a first edge portion of the mask layer adjacent to the first region or a second prescribed region of a second edge portion of the mask layer adjacent to the second region, and a concave portion is formed in at least either the first prescribed region or the second prescribed region of the mask layer in association with formation of the combined trench.
In the method of manufacturing a semiconductor device according to the fourteenth aspect, the concave portion is formed in at least either the first prescribed region or the second prescribed region of the mask layer in association with formation of the combined trench for defining a protrusion, while the thickness of the second oxide film located on this protrusion is reduced when the second oxide film is formed by high-density plasma CVD and the protrusion is also polished when performing planarizing by chemical mechanical polishing, whereby the edge portion of the mask layer can consequently be brought into a shape thinned with a step.
According to a fifteenth aspect of the present invention, the method of manufacturing a semiconductor device further comprises a step of performing annealing in a nitrogen atmosphere, a hydrogen atmosphere or an argon atmosphere in a stage at least either before or after formation of the first oxide film.
In the method of manufacturing a semiconductor device according to the fifteenth aspect, crystallinity on the outermost surface of the SOI layer can be improved by performing annealing in a nitrogen atmosphere, a hydrogen atmosphere or an argon atmosphere before formation of the first oxide film, while stress on the SOI layer following heat treatment can be relaxed when performing the said annealing after oxidation.
According to a sixteenth aspect of the present invention, a method of manufacturing a semiconductor device comprises steps of (a) preparing an SOI substrate comprising a silicon substrate, a buried oxide film arranged on the silicon substrate and an SOI layer arranged on the buried oxide film, (b) forming an oxide extension layer on the SOI layer, (c) forming a mask layer having a prescribed opening pattern on the oxide extension layer, (d) forming a trench by selectively removing the SOI layer through the mask layer without passing through the SOI layer from the surface, (e) forming a first oxide film on the inner wall of the trench by thermally oxidizing the inner wall of the trench and the oxide extension layer, (f) forming a resist mask having an opening at a first region between a prescribed position at least on the bottom surface of the trench and a first side wall surface in a brachydirectional section, and covering a second region between at least the prescribed position and a second side wall surface in the brachydirectional section, (g) removing the trench to reach the buried oxide film through the resist mask for forming a combined trench having a portion corresponding to the second region being a partial trench having the SOI layer on its lower portion and a portion corresponding to the first region being a full trench passing through the SOI layer and (h) forming a trench isolation oxide film combinationally having a full trench structure reaching the buried oxide film through the SOI layer and a partial trench structure having the SOI layer on its lower portion by filling up the combined trench with a second oxide film.
In the method of manufacturing a semiconductor device according to the seventeenth aspect, a trench isolation oxide film combinationally having a full trench structure reaching the buried oxide film through the SOI layer and a partial trench structure having the SOI layer on its lower portion can be obtained. This trench isolation oxide film has such a contour shape that its upper edge portion projects into the surface of the SOI layer in the form of a bird""s beak while the contour shape is similar on the left and right edges in a brachydirectional section.
An object of the present invention is to provide a semiconductor device including a MOS transistor having a gate oxide film prevented from dielectric breakdown without increasing the thickness thereof and a method of manufacturing the same.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.